Resolving missing coverage using simulink design verifier and not by using simulink test

 I have a complex stateflow subsystem which has given me less coverage while using simulink coverage and simulink design verifer license. Is there any formal method to resolve the missing coverage without using simulink Test license nor do I use reactis license

My approaches so far
I have even tried generating multiple .cvt files (coverage files) but thats not helping me to maximise the coverage.
Does entering range of min and max values of inputs help to maximise the coverage.

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Simulink Test will help you manage and construct a test-suite - I am not sure it will help you in achieving coverage on its own. For example, Simulink Test can help if you want to manually author test-case in additio to auto-generating test-cases from Simulink Design Verifier, or if you want to manage test-suites across multiple components (models/subsystems etc.), and automate test-execution, coverage measurement etc.
Have you tried identifying dead-logic in the state-chart? Are there "unsatisfiable" objectives in the chart? Have you analyzed the chart for design-errors?
Entering min-max values for inputs would make the formal analysis problem more tractable, it can convert some "undecided" objectives into "satisfied". But you do need to be careful that the ranges reflect the actual intended usage of the stateflow chart. If you over-constrain the ranges, some objectives in the chart may become unsatisfiable.


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